PIC18F4450-I/PT【PDF 126/241 页】IC PIC MCU FLASH 8KX16 44TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3854

122页 123页 124页 125页 [126页]127页 128页 129页 130页

211

XMEGA A [MANUAL]

8077I–AVR–11/2012

19.5.1.1 Case M1: Arbitration lost or bus error during address packet

If arbitration is lost during the sending of the address packet, the master write interrupt flag and arbitration lost flag are

both set. Serial data output to the SDA line is disabled, and the SCL line is released. The master is no longer allowed to

perform any operation on the bus until the bus state has changed back to idle.

A bus error will behave in the same way as an arbitration lost condition, but the error flag is set in addition to the write

interrupt and arbitration lost flags.

19.5.1.2 Case M2: Address packet transmit complete - Address not acknowledged by slave

If no slave device responds to the address, the master write interrupt flag and the master received acknowledge flag are

set. The clock hold is active at this point, preventing further activity on the bus.

19.5.1.3 Case M3: Address packet transmit complete - Direction bit cleared

If the master receives an ACK from the slave, the master write interrupt flag is set and the master received acknowledge

flag is cleared. The clock hold is active at this point, preventing further activity on the bus.

19.5.1.4 Case M4: Address packet transmit complete - Direction bit set

If the master receives an ACK from the slave, the master proceeds to receive the next byte of data from the slave. When

the first data byte is received, the master read interrupt flag is set and the master received acknowledge flag is cleared.

The clock hold is active at this point, preventing further activity on the bus.

19.5.2 Transmitting Data Packets

Assuming case M3 above, the master can start transmitting data by writing to the master data register. If the transfer was

successful, the slave will signal with ACK. The master write interrupt flag is set, the master received acknowledge flag is

cleared, and the master can prepare new data to send. During data transfer, the master is continuously monitoring the

bus for collisions.

The received acknowledge flag must be checked by software for each data packet transmitted before the next data

packet can be transferred. The master is not allowed to continue transmitting data if the slave signals a NACK.

If a collision is detected and the master loses arbitration during transfer, the arbitration lost flag is set.

19.5.3 Receiving Data Packets

Assuming case M4 above, the master has already received one byte from the slave. The master read interrupt flag is set,

and the master must prepare to receive new data. The master must respond to each byte with ACK or NACK. Indicating

a NACK might not be successfully executed, as arbitration can be lost during the transmission. If a collision is detected,

the master loses arbitration and the arbitration lost flag is set.

19.6

TWI Slave Operation

The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave data and address/stop

interrupts. Interrupt flags can also be used for polled operation. There are dedicated status flags for indicating

ACK/NACK received, clock hold, collision, bus error, and read/write direction.

When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle data, and will in

most cases require software interaction. Figure 19-13. shows the TWI slave operation. The diamond shapes symbols

(SW) indicate where software interaction is required.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式